1. Field of the Invention
This invention relates to an IC circuit for use in the pulse width modulator for motor drive circuitry such as the one in office or industrial equipment, which may be implemented with bipolar process ICs.
2. Description of the Related Art
The conventional servo motor for use in office equipment or the like is driven through a drive circuitry illustrated in FIG. 6, wherein the motor 55 is rotationally driven through an output circuit 54 in a pulse width modulation drive system 53 in response to speed instruction signals externally applied to the drive system 53 through a terminal 52. Rotation of the motor 55 is under control by energization sensor signals 56 sensed from the motor 55 and fed back to the drive system 53. The output circuit of a pulse width modulation drive system is usually a discrete circuit due to its simplicity in circuit arrangement. An example of such discrete output circuit of pulse width modulation is illustrated in FIG. 4 and discussed referring to FIG. 4.
Referring to FIG. 4, the base of a transistor 29 is connected to the collector of a transistor 31 and to the collector of a transistor 30 through a resistor 35, with the base of the transistor 30 being connected to a power supply line 49 through a resistor 36 and to a terminal 45. The base of the transistor 31 is connected to a terminal 46 through a resistor 37 and to the power supply line 49 through a resistor 41. The emitters of the transistors 29 and 31 are connected to the power supply line 49, while the counterpart of the transistor 30 is connected to another power supply line 50.
The base of a transistor 32 is connected to the collector of a transistor 34 directly and to the collector of a transistor 33 through a resistor 38, while the base of the transistor 34 is connected to the power supply line 49 through a resistor 39 and to a terminal 48. The base of the transistor 33 is connected to a terminal 47 via a resistor 40 and to the power supply line 49 via a resistor 42. The emitters of the transistors 32 and 34 are connected to the power supply line 50, with the emitter of the transistor 33 being connected to the power supply line 49.
The collectors of the transistors 29 and 32 are led together to a terminal 51 which serves as the output terminal of this circuit arrangement. Connected to the output terminal 51 is the anode of a diode 43 whose cathode is connected to the power supply line 49. The anode of another diode 44 is connected to the power supply line 50, with its cathode being connected to the output terminal 51. It is noted that the transistors 29, 31 and 33 are of the PNP type and the transistors 30, 32 and 34 are of the NPN type.
The circuit arrangement as discussed above will work as follows: The terminals 45, 46, 47 and 48 receive signals as shown in FIG. 5. At time (a), the circuit arrangement assumes the following operation mode. When a High signal is applied to the terminal 45, the transistor 30 turns ON and the transistor 29 also turns ON. The potential Vout at the output terminal 51 increases to the level corresponding to the potential in the power supply line 49 (leading to Vcc) minus the saturation voltage Vce (sat) of the transistor 29. EQU Vout=Vcc-Vce (sat)
On the other hand, the transistor 33 turns OFF with no supply of current to the base of the transistor 32, since a High signal has been applied to the terminal 47. Further, because the High signal has also been applied to the terminal 48, the transistor 34 turns ON to short the base-to-emitter path of the transistor 32 and turns OFF the transistor 32.
At time (b), the terminal 45 receives a Low signal to turn OFF the transistor 30, with no current supply to the base of the transistor 29 as a consequence. The terminal 46 also receives a Low signal, so that the transistor 31 turns ON to short the base-to-emitter path of the transistor 29 and turn OFF the transistor 29 instantaneously.
On the other hand, the transistor 32 remains OFF because the terminals 47 and 48 assume the same status as at time (a). At time (c), a Low signal is applied to the terminal 47 to turn ON the transistor 33 with a current supply to the base of the transistor 32 as a consequence. The terminal 48 receives a Low signal, so that the transistor 34 turns OFF, with the base-to-emitter path of the transistor 32 brought into open state. The result is that the transistor 32 turns ON. The transistor 29 remains OFF because the terminals 45 and 46 are in the same state as at time (b). In this situation, the potential at the output terminal 51 equals the saturation voltage Vce (sat) of the transistor 32. EQU Vout=Vce (sat)
At time (d), the terminal 47 receives a High signal to turn OFF the transistor 33 with no current supply to the base of the transistor 32. The terminal 48 also receives a High signal, so that the transistor 34 turns ON to short the base-to-emitter path of the transistor 32 and turn OFF the transistor 32 immediately.
It is clear from the above explanation that there is a certain period of time during which both the transistors 29 and 32 are OFF, that is, a break period where current is prevented from flowing through the transistors 29 and 32. The diodes 43 and 44 are flywheel diodes which form a circuit for discharging the energy stored in the wiring while the output terminal 51 is loaded with an inductance. For example, when output current is flowing out of the output terminal 51, current is flowing through the power supply line 49, transistor 29, output terminal 51 and inductance load while the transistor 29 is ON. In this condition, if the transistor 29 is turned OFF, current will tend to continue flowing out of the output terminal 51 due to the inductance load. At this moment, however, the diode 44 turns ON, permitting current to flow through the power supply path 50 and the output terminal 51 and the inductance load. If current flows into the output terminal 51, the transistor 32 will turn OFF and the diode 43 will turn ON.
The above circuit arrangement faces difficulties when it is to be implemented as an IC device in that the transistor 29 on the side of the output terminal 51 is of the PNP type with a smaller current capacity per unit area than the NPN type and must have a larger chip area in order to meet the requirement of a current flow between 1 and 2 amperes. Further, due to the use of the transistor 32 of the NPN type on the side of the output terminal 51 which is different in type from that of the transistor 29, the circuit arrangement presents another problem in that differences in current amplification factor h.sub.EE and switching speed make it difficult to balance the circuit arrangement.